1. Field of the Invention
The present invention relates to a potential detecting circuit which determines whether a comparison potential reaches a prescribed detection level or not.
2. Description of the Background Art
FIG. 20 is a circuit diagram of a configuration of a potential detecting circuit in the background art. The background-art potential detecting circuit includes PMOS transistors 6a to 6d connected in series between a comparison potential VL and a ground level, and an inverter 7. The transistors 6a to 6d are each diode-connected. The inverter 7 consists of AMOS transistor 7a and an NMOS transistor 7b. The input of the inverter 7 (the gates of transistors 7a and 7b) is connected to a node NA which is the drain of transistor 6c placed third from the comparison potential VL.
In the background-art potential detecting circuit, a level detection signal GE of H-level is generated from a node NB when a potential at the node NA is lower than the logical threshold value of the inverter 7, and the level detection signal GE of L-level is generated when the potential at the node NA is higher than the logical threshold value of the inverter 7.
Since the background-art potential detecting circuit has the above configuration, the logical threshold value of the inverter 7 varies with a variation of a power supply potential .sup.V CC, to disadvantageously render the level detection signal GE unstable.
Moreover, a detection level for the comparison potential VL is disadvantageously not controllable since the comparison potential VL is applied to the node NA through the diode-connected three transistors 6a to 6c.
For the same reason, the detection level of the potential detecting circuit varies with a change of an operating temperature since the change of the operating temperature causes a variation in threshold voltage of the transistors 6a to 6c. In the potential detecting circuit, the variation in threshold voltage increases threefold since the three transistors are connected in series.